The present invention relates to the field of semiconductor devices such as field-effect transistors of the "double diffused MOS" type known under the name "vertical operation DMOS" and intended to be used for power amplification or switching and more particularly to a process for manufacturing this type of transistor as well as the transistor obtained by this process.
Field-effect transistors have up to present been used principally as microcomponents in integrated circuits. The structure of such circuits was principally formed from symmetrical elements insulated from each other and having electrical performances adapted to the generally desired rapidity-consumption compromise.
However the characteristics proper to field-effect transistors, short cut-off time, linearity, high thermal stability, allow an increased field of application to be contemplated for these transistors reserved up to present for bipolar transistors particularly in the field of amplification, rapid switching and power switching or control.
Vertical-operation DMOS transistors such as shown in section in FIG. 1 comprise on a wafer of a semiconductor material 1, such as silicon, a structure formed from parallel fingers 41 forming the grid of the transistor, the grid being insulated from the wafer of semiconductor material by a silicon oxide layer 2. The parallel fingers 41 are formed by polycrystalline silicon. The wafer of semiconductor material 1 comprises, between the fingers forming the grid, interfitting zones 6 and 8 forming respectively the channel-forming zones and source regions of the transistor. By way of example, the silicon wafer has a type N conductivity, channel-forming zones 6 are diffused of type P and the source regions 8 are N.sup.+ doped. The silicon wafer also comprises a drain region 120 of N.sup.+ conductivity type and a metallization 9 insulated from the grid fingers 41 of a silicon oxide layer 5 developed by thermal growth from the polycrystalline silicon forming grid fingers 41. The metallization 9 forms the connection for the source regions.
As shown in FIG. 1, the structure, with respect to this type of transistor, is developed in the form of fingers perpendicular to the plane of this section. For a given dimension of these fingers in a direction perpendicular to the plane of this section, the conductance per unit area of such devices is inversely proportional to the pitch p of the network of interfitting fingers. This pitch is written p=G+S+2a where G is the lateral dimension of each finger, S the laterl dimension of the source contact and a the positioning tolerance of the source contact with respect to the grid electrode. In transistors of this type, the conductance per unit area is proportional to the lateral dimension of the channel-forming zone formed by the diffusions. For an interfitting structure, the lateral dimension of the channel-forming zone increases when pitch p of the structure decreases, the conductance per unit area being in this case limited particularly by the existence of the positioning tolerance a of the contact in relation to the grid.
The process of the invention aims at providing a field-effect transistor in which the positioning tolerances of the source contact are substantially abolished.
Another aim of the invention is to provide a process for manufacturing a field-effect transistor allowing improved control of the doping of the source region.
Another aim of the present invention is to provide by the abovementioned process a transistor of the vertical-operation DMOS type particularly adapted to power switching.